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Extended display identification data (EDID) is a companion standard; it defines a compact binary file format describing the monitor's capabilities and supported graphics modes, stored in a read-only memory (EEPROM) chip programmed by the manufacturer of the monitor. The format uses a description block containing 128 bytes of data, with optional extension blocks to provide additional information. The most current version is Enhanced EDID (E-EDID) Release A, v2.0.
DDC changed the purpose of the ID pins to incorporate a serial link interface. However, during the transition, the change was not backwards-compatible and video cards using the old scheme could have problems if a DDC-capable monitor was connected. The DDC signal can be sent to or from a video graphics array (VGA) monitor with the I2C protocol using the master's serial clock and serial data pins.
DDC1 is a simple, low-speed, unidirectional serial link protocol. Pin 12, ID1 functions as a data line that continuously transmits the 128-byte EDID block, and the data clock is synchronised with vertical sync, providing typical clock rates of 60 to 100 Hz.
The most common version, called DDC2B, is based on I²C, a serial bus. Pin 12, ID1 of the VGA connector is now used as the data pin from the I²C bus, and the formerly-unused pin 15 became the I²C clock; pin 9, previously used as a mechanical key, supplied +5V DC power up to 50mA to drive the EEPROM, this allows the host to read the EDID even if the monitor is powered off. Though I²C is fully bidirectional and supports multiple bus-masters, DDC2B is unidirectional and allows only one bus master - the graphics adapter. The monitor acts as a slave device at the 7-bit I²C address 50h, and provides 128-256 bytes of read-only EDID. Because this access is always a read, the first I²C octet will always be A1h.
DDC/CI (Command Interface) standard was introduced in August 1998. It specifies a means for a computer to send commands to the monitor, as well as receive sensor data from the monitor, over a bidirectional link. Specific commands to control monitors are defined in a separate Monitor Control Command Set (MCCS) standard version 1.0, released in September 1998.
Earlier DDC implementations used simple 8-bit data offset when communicating with the EDID memory in the monitor, limiting the storage size to 28 bytes = 256 bytes, but allowing the use of cheap 2-Kbit EEPROMs. In E-DDC, a special I²C addressing scheme was introduced, in which multiple 256-byte segments could be selected. To do this, a single 8-bit segment index is passed to the display via the I²C address 30h. (Because this access is always a write, the first I²C octet will always be 60h.) Data from the selected segment is then immediately read via the regular DDC2 address using a repeated I²C 'START' signal. However, VESA specification defines the segment index value range as 00h to 7Fh, so this only allows addressing 128 segments × 256 bytes = 32 KiB. The segment index register is volatile, defaulting to zero and automatically resetting to zero after each NACK or STOP. Therefore, it must be set every time access to data above the first 256-byte segment is performed. The auto-reset mechanism is to provide for backward compatibility to, for example, DDC2B hosts, otherwise they may be stuck at a segment other than 00h in some rare cases.
Some KVM switches (keyboard-video-mouse) and video extenders handle DDC traffic incorrectly, making it necessary to disable monitor plug and play features in the operating system, and maybe even physically remove pin 12 (serial data pin) from the analog VGA cables that connect such device to multiple PCs.
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