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The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a stacked structure of semiconductor chips.
Description of the Related Art
Recently, in order to meet the demand for higher performance of information processing systems, high-performance information and communication devices have been mounted on small-sized electronic devices including mobile phones.
In a mobile phone, it is important to reduce the size of an electronic device so as to reduce the size of the mobile phone, in particular, a base band circuit and a power supply circuit are demanded to be reduced in size and in power consumption.
In order to reduce the size of a base band circuit and a power supply circuit, it is possible to reduce the size of a semiconductor device in which these circuits are mounted, and to reduce the size of a package that houses the semiconductor device.
It is known that a package size can be reduced by the use of a quad flat non-leaded (QFN) package or a thin quad flat non-leaded (TFN) package instead of a conventional lead-leaded package.
For example, in the QFN package and the TFN package, a semiconductor chip having a semiconductor circuit is disposed on a lead frame (substrate) or a heat spreader, and the semiconductor chip is sealed with a sealing resin. In the QFN package and the TFN package, a distance between the lead terminals is shortened so as to reduce the size of the package.
The cost of a lead frame or a heat spreader is high, and in the case of a thin substrate, the warp amount of the substrate increases, which leads to the cracking of a sealing resin. Therefore, in the QFN package and the TFN package, it is difficult to sufficiently reduce the size of the package, and the cost is high.
Therefore, in Japanese Patent Application Laid-Open No. 2013-114191, a semiconductor device having a stacked structure of semiconductor chips 0b46394aab